1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
A flash memory and a ferroelectric memory are well-known as nonvolatile memories capable of storing information even after a power supply is turned off.
In the nonvolatile memories, the flash memory includes a floating gate that is embedded in a gate insulating film of an insulated gate field effect transistor (IGFET), and stores information by accumulating electric charges indicating recording information in this floating gate. However, there is a drawback in that such a flash memory requires a relatively high voltage in order to flow the tunnel current to the gate insulating film at the time of writing and erasing the information.
On the other hand, the ferroelectric memory, which is also referred to as FeRAM (Ferroelectric Random Access Memory), stores information by utilizing a hysteresis characteristic of a ferroelectric film provided in a ferroelectric capacitor. The ferroelectric film causes polarization in response to the voltage applied between upper and lower electrodes of the capacitor, and spontaneous polarization becomes residual even after the voltage is removed. When the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. By bringing the direction of the polarity to correspond to “1” and “0”, the information is written in the ferroelectric film. The voltage required for the FeRAM to carry out writing is lower than that for the flash memory to carry out writing. In addition, there is also an advantage in that the FeRAM is capable of writing at a higher rate than the flash memory is.
The FeRAM is classified broadly into two categories of a stack type and planar type based on its structure. In the latter planar type, the planar shape of the capacitor tends to be large since a MOS (metal oxide semiconductor) transistor formed on a semiconductor substrate and the lower electrode of the capacitor are electrically connected via metal interconnects on the upper side of the capacitor.
In contrast, in the stack FeRAM, the lower electrode of the capacitor is formed directly on a conductive plug connected to a source/drain region of the MOS transistor, and the lower electrode and the MOS transistor are electrically connected via the conductive plug. With this structure, it is possible to make the planar shape of the capacitor smaller compared with the planar FeRAM so that the minimization of FeRAM required for future is brought about.
It is required for the capacitor dielectric film provided with the stack FeRAM that crystallinity be not deteriorated and an excellent ferroelectric property be provided even when the FeRAM is minimized.
It should be noted that the related technologies are disclosed in Japanese published unexamined applications No. 2004-146772, No. Hei 11-330411, Hei 10-340871, and Hei 7-22578.